1461179970-9f555379-eaa5-48d6-abbf-522b049b6fe9

A multi-ported orthogonal data memory for effecting a corner-turning function, where for example data input as a sequence of bit-parallel word-serial data transfers are converted to data output in a bit-serial, word-parallel fashion, is described. These values satisfy the relationship of EVT2EVT1. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. Each optimal line break scheme is calculated by minimizing the total of a penalty value of a current line and all preceding penalties of all preceding lines. The multiplexer provides values for the codes, the values for the codes being a function of 2trunc. The latch interlocks with a stop on the coupling body to provide a passive lock when the arm is closed.