A disk processing system having a plurality of processing chambers, a load chamber comprising a heater, and a disk transport system coupled to the plurality of processing chambers and the load chamber to transport a disk there among. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The circuit is operable to enable the controller to operate when the voltage supplied by the cell to the controller is below an operating voltage threshold off the controller. For each of the peer documents, a label is generated by choosing the longest-match anchor text of the linking documents.