A structure and method of manufacturing a CMOS device where the Coplanar wave guide lines are formed above the top metal lines. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. An interlevel dielectric layer 140 encapsulates biased charge control electrodes 142a and they control the electric field within the area of the drift region 14 between P-base 122 and the N drain region 132 to increase the reverse breakdown voltage of the device.