Improved responses can be generated to scan patterns for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. Instead of the decoration, a dummy part is temporarily placed in the hole pierced in the external element, and the galvanic deposition is then carried out. In certain embodiments, the process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit’s resistance andor the minimization of the sub-circuit’s capacitance. The combination assembly significantly reduces the force applied to the electrical box by electrical equipment andor devices connected to wirescable received by the electrical box as compared to prior art mounting brackets by distributing the force to a larger surface area of the mounting bracket and truss joist.