Methods and apparatus relating to very large scale FET arrays for analyte measurements. In the sipes, protrusions are formed on a first sipe wall surface of mutually opposing sipe wall surfaces and recesses that engage with the protrusions are formed on a second sipe wall surface. The spacer is coupled to the active surface of the first semiconductor die entirely within the first and second rows of bond pads of the first semiconductor die, the spacer overhanging at least one side of the first semiconductor die. One of the core housing and plate-like face member constitutes a drawing faceplate which is formed to be transparent or semi-transparent.