A computer system includes a memory controller coupled to a memory module containing several DRAMs. The DC current is either a constant value DC current, or a DC current that swept andor stepped from a first value toward a second value in a manner whereupon the electric field and, hence, a DC voltage induced across the dielectric layer increases as the DC current approaches the second value. Coupling point is prepared at upper section, then lower section, and upper section then lower section alternately. The first communication packet is processed through the first plurality of communication modules based upon the ordering specified in the first event list.