A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. A system for detecting the unauthorized access points comprises a monitoring client simulating a user and detecting available access points. These dielectric reflectors are disposed in such a way as to allow selection of preferred low order modes and suppression of parasitic modes while allowing a high cavity Q factor for preferred modes. The first receiving space has an opening configured for passing the electronic products therethrough.