The current invention includes a tube with a helical fin extending from the tube’s outer surface. The logic signal generator generates a first logic signal and a second logic signal that have the same period but have different logic level transition timing. The disabling step may be accomplished, for example, by disabling the buffering of an address of the data unit or stalling the second memory. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential.