A pixel data transfer controller reads color pixel data including pixel data pertaining to \u201cm\u201d color elements from a memory through a first bus having an \u201cn\u201d-byte width, and transfers the color pixel data to an image processing circuit through second buses which are associated with the respective color elements. The receiver can be on for a short period, off for a short period if no preamble pulses from a remote control device are received, on for a short period, and then off for a longer period until the next cycle. Additionally, the system and method increases efficiency by distributing recordings to scoring users for scoring during times of low utilization or during previously scheduled scoring time blocks. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.