A data processing circuit comprises a register file having read ports and write ports. The bracket includes a rear wall coming to rest on a buccal or lingual tooth surface; and two guide surfaces running at right angles to one another, for guiding an archwire with a rectangular cross section, wherein the two guide surfaces are arranged distanced to the rear wall. The first mixer comprises first and second mixing stages for mixing an input signal with the first and second commutating signals and a summer for summing the mixer stage output signals. In addition, the capping layer is formed over at least a portion of the metallization layer and is in electrical contact with the metallization layer. Using the same primary process for measuring suds lock, load size can also be ascertained.