A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The NT-CDPSDP unit includes a first electrode disposed between two dielectric layers, wherein the first electrode and dielectric layers having at least one opening defined therethrough. The winding apparatus uses a winding motion to wrap the wrapping material around the root material and carrier line, securing the root material to the carrier line and creating the \u201croot rope. To limit the expense of manufacturing the system, the exterior of the canisters are identically molded and the bottom caps of the canisters are integrally molded to the body of the canisters, also eliminating one possible leakage point. The emergency respondence warning system also warns of the approach of multiple emergency vehicles. Also described is a method of manufacturing a corresponding mattress.