In an embodiment, at least one pair cleats is provided. The n-FET is provided with a compressive dielectric stressor, while the p-FET is provided with a tensile stressed dielectric. The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate.