A technique for managing the utilization of processing resources involves filtering packets that are sent to a CPU for learning before allowing the packets to reach the CPU. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The second node provides a response to the first node that transfers the ordering point to the first node in response to the request for the data. The ripple cancellation circuitry uses a switching signal that is provided by the switching power supply to generate the ripple cancellation signal. The gradient path can be determined from the gradient of the potential field by quadric error-based surface simplification of a surface mesh representing a surface of the gamut.