An abutted-pin hierarchical physical design process is described. Also disclosed are methods for their preparation and methods for their use in introducing one or more fluorine atoms into target substrate compounds. A combination of the first and second capacitors functions as a first power decoupling capacitor, and a transistor disposed in the peripheral area functions as a second power decoupling capacitor. Changes made to business center information at the portal are made in the business center’s server, allowing the business center portal to be used to manage the business center’s own servers and management system. For each output phase, each identical cell has a diode input rectifier circuit, an active harmonic filter, an intermediate-circuit capacitance, and a three-point DCAC converter on the output side. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an \u201cL\u201d shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.