Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer. The test circuit, when it obtains differences based on pieces of fail-information sequentially obtained with a wrong-determination result at the time of holding the specific fail-information as a base point, sequentially adds subsequent differences to the specific fail-information to decompress subsequent pieces of fail-information.