A stencil assembly for use in depositing filling onto wafers includes a stencil tube defining a lengthwise passage for flow of filling, the stencil tube including an outer surface, and at least two axially spaced apart filling outlets passing through a wall of the tube. According to the present invention, a gate electrode is a multilayer, and a hat-shaped gate electrode is formed by having the longer gate length of a lower-layer gate electrode than that of an upper-layer gate electrode. The FRC portion includes a motion vector detecting portion for detecting a motion vector between the frames of the input image signal, an interpolating vector evaluating portion for allocating an interpolating vector between the frames based on the motion vector information, and an interpolating frame generating portion for generating an interpolating frame from the interpolating vector. The content of the amorphous polyamide in the barrier layer is adjusted to 15 to 25 wt %.