A graphics processor includes a graphics pipeline having a set of tap points. The alleviation area is provided between an intersection of a second axis perpendicular to the first axis and passing through the center of the mirror reflecting surface and an edge of the mirror reflecting surface, and at least one of the torsion bars. One module includes a linear array of candle receiving cells with an equal number of projections beneath them, each cell and its associated projection being structurally related to allow combining a plurality of such modules together in a variety of arrangements. By using the generated signal to provide a lock if certain conditions arise, adjustment errors resulting from duty cycle distortion and clock skew can be minimized. A closure member is positioned adjacent to the aperture.