A fault-tolerant maintenance bus architecture provides dual maintenance buses interconnecting each of a plurality of parent circuit boards. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. The vectors are each provided in separate portions as a first portion and a second portion. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. This uses a non-calibrated splitter and less than all four of the Stokes parameters.