A multi-processor includes multiple processing clusters for performing assigned applications. Each transmissive pixel is configured to receive a transmissive pixel voltage transmitted from one of the data lines and displays a first gray level related to the transmissive pixel voltage. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. A first series circuit has a fifth switch element connected in parallel with the first switch element. After brake engagement, the shutoff valve is switched to shut-off position decoupling the actuator from the supply line; the supply valve is switched to flow-enabled position placing the supply line in communication with the pressure sink.