A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock. Also disclosed is a method for forming a resist pattern using the developing solution. A handset is issued to a user, the detection system being arranged to detect the handset when it is within the coverage zone and to record the user of the handset as being in the queue. The wire is pulled up and cut at the wire bent portion. Code delay and carrier phase and frequency errors are used to update the code and carrier tracking loop filters.