1460952729-9949b8f4-183c-4beb-b571-c56b097f7e19

A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. In one embodiment of the invention, a CML buffer having true and complementary data outputs drive the differential data signal onto the positive and negative signal lines of the differential pair. The ESD circuit includes a nanotube switch electrically having a control. Thus, it is possible to prevent the retention characteristics of the ferroelectric capacitor from being deteriorated due to the stress applied by the first interconnection layer to the ferroelectric capacitor. The result is improved operability.