A clock network comprises a clock distribution path coupled to a circuit. The at least one second electrode is spaced from the at least one first electrode. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. This improves workability in reading and writing individual information without error, traceability to assure quality of semiconductor devices, and analysis of defects in semiconductor devices. An optional restraint bar safety mechanism is also provided. First and second wire capturing mechanisms are situated in corresponding first and second openings defined by first and second receptacles, respectively, each wire capturing mechanism being configured to restrict movement of a respective conductor once inserted therethrough.