A semiconductor device with an MOS transistor gate electrode in a stacked structure comprising a silicon layer, a metal silicide layer, a reaction barrier layer such as a metal nitride layer and a metallic layer formed from the bottom upwards has an increased circuit performance owing to a gate resistance-reducing effect. The dual panel architecture allows pipelining of pixel readout and column readout operations to improve the imager’s frame rate. As a result, the precision of the pointer’s movement for the purpose of menu navigation can be enhanced for user convenience. The configuration may be changed, such as screen segment selection, during a preview of it.