A memory device includes a gate stack on a substrate. An elongated handle extends from a first surface of the base for positioning the base in a chassis. A whole length of the second capillary wick is longitudinally joined with the first capillary wick. Photolithographic techniques are used to generate plated-through-hole plugs of controlled, variable depth in the through-holes before first and second conductive vias are respectively plated onto the first and second through-holes. A return address identifier determines the pointed-to as a return address when the one or more bytes constitute the call instruction.