A column redundancy architecture for arrayed parallel processor devices is disclosed. It includes a pan as well as a cover with linearly disposed bores. Implementations based on the Enterprise JavaBean specification are disclosed for three illustrative embodiments of the present invention. One of the arms may be deformable. Performance via a process guide may be interactive in that the technician may provide input, or automatedsemi-automated by analyzing various information collected by the marking apparatus with respect to the ticket information andor other available information germane to the operation.