An image processing device of the present invention comprises a bus, an image processing module group, a controller, a memory, and a format converting module. A device isolation structure is set up in the substrate to define an active region. The first coil seat includes a first bottom plate having a first central opening, a plurality of first outer teeth and a plurality of first inner teeth. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal. A plurality of grooves that are distributed around the circumference and extend in the direction of flow are arranged within the wall area of the intake channel.