A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces resistance on the bitline contact. The controller is operable to store a fixed code. The method may include inserting a software package into the image. As more RAM side rows are accessed, the hit bitline drops lower in voltage.