An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. Embodiments of the present disclosure provide a system and associated processes for consolidating and replacing various forms of payment with a single payment system. Myocardial electrical stability is then analyzed using frequency domain techniques that are tailored to the patterned pacing sequence used to pace the patient’s heart. The housing includes a drive housing unit connected to a handle having a rod shape. The cache may further include way locking control circuitry which indicates whether or not one or more ways is locked. Upon receiving a request to securely erase a data page from the memory, one or more of the memory cells in a group that stores the data page are re-programmed using a second programming configuration having a second storage speed that is faster than the first storage speed.