A system for caching data in a distributed data processing system allows for the caching of user-modifiable data across one or multiple entities in a manner that prevents stale data from being improperly used. The bias circuit compensates odd-order distortion processes by detecting the power in the input signal and providing a dynamic adjustment to a bias stimulus for the power-amplifying device within a time scale of the modulation envelope. Thus, the number of available output speeds excluding neutral is given by 2n, where n=2. Links of the first parallelogram linkage and links of the second parallelogram linkage are configured to rotate while being in a restrained state of 90\xb0 at pivots of both ends of the common link of the first and second parallelogram linkage, respectively. A serial bus connects electronic modules within the apparatus and also connects the apparatus to an external controller.