A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test. A \u03bb2 compensation film and a \u03bb4 compensation film are disposed on outer surfaces of the color filter array panel and the TFT array panel, respectively. Tape or thread can be used to connect the artery to the retractor with a holder. Then, onoff of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated.