A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. After being stored in the logical registers, the data elements are then treated as matrix elements. A dielectric material is deposited on the first surface of the silicon substrate and into the plurality of grooves. At least one color element is octagonal, having four straight sides and four beveled sides. The mobile communication terminal reduces a paging channel monitoring time by entering a sleep mode or a wake-up mode at an arbitrary timing instead of a PN code rollover period, resulting in the increment of a standby time of the terminal.