A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. Each universal logic cell includes first to seventh nodes formed in a top layer of common interconnection layers which are allocated to the universal logic cells. At least one of the plurality of ribs has a leading portion and a trailing portion, the leading portion comprising a first matrix material impregnated with super abrasive particles and the trailing portion comprising a second matrix material impregnated with super abrasive particles, wherein the first and second matrix materials differ from each other.