A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The two switching elements perform a switching operation according to a control signal to control an output voltage. The aft-body is preferably composed of a crown portion, a sole portion and optionally a ribbon section. The test system controller can provide compensation for the base to emitter voltage drop of the emitter follower transistor. The technique can be performed as a remedial treatment or in new completions, but it is particularly useful in workover treatments for existing wells.