Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. In one embodiment, the transistor includes a sourcedrain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the sourcedrain. Each of the first layer 2 and the second layer 3 contains a polyvinyl acetal resin and a plasticizer.