1459913140-ad24be0f-0999-4a03-9963-50ef28f472d8

A semiconductor memory device is provided with: first and second access PMOS transistors formed on N well regions; first and second driver NMOS transistors formed on a P well region; a word line connected to the gates of first and second access PMOS transistors; and first and second bit lines connected to the sources of first and second access PMOS transistors, respectively. The storage layer produces a relatively large spherical aberration for a protection layer thickness error. An estimated network impulse response is estimated from the reflectometry response. The user may retrieve the information from the navigation system using the identifier.