1459915087-7f3db01e-6c5c-4d47-9c90-f74922aa1d6e

Digital delay locked loops which generate fixed angle delayed clock signals based on a reference clock signal and that accounts for clock signal delay. The cathode comprises a closed chamber consisting of a cap supporting an emitting part of the cathode and a dish-shaped skirt having an internal surface which is concave so as to reflect, by radiation, the thermal energy stored in the skirt walls, towards that region of the cap supporting the emitting part. In an alternative embodiment, the bottom electrode andor bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. A desired signal quality for each of the plurality of data streams is determined based on the corresponding priority.