A target audit methodology to provide a transaction-based detail of errors in an environment with a high volume of transactions. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. Opposing sidewalls extend upwardly from the rear portion of the base. The logic circuit maintains the order of the requests in an efficient manner that is transparent to the processor. The support structure includes an armrest connected to a flexible linkage or articulated or pivoting assembly, which includes a tensioning element such as a spring.