The invention relates to a design analysis technique for a test pattern analysis of chips via automatic test equipment or a circuit simulation to detect potential design weakness or abnormal behavior in real customer application faults. Holes are formed at the crossing portion between the cathode wiring line layer and the gate wiring line layer so as to penetrate through the insulating layer, and resistive layer and an emitter layer are provided in the holes. At least one additional and parallel stratification source to the signatures obtained from group of sample sis provided, the at least one additional and parallel stratification source to the signatures being independent from the signatures and generates a second set of stratification values. The values stored in the lookup memory are approximated based upon a predetermined value to prevent overflow in the fixed point multiplication.