The disclosed technology uses a visibility function within a network environment that includes a set of nodes. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit applies a high impedance to the transmission path. The rim of the bell fits into the incision located in the inner section of the foam ring. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.