A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A common source line is arranged to be shared by the memory blocks. On the basis of the information from region designation calculator 27, data classifier 24 classifies data, after analogue-to-digital conversion, into data of regions in which there is a path and data of regions in which there is no path.