A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. The system and method provide for analyzing MAC addresses and source IP addresses at the datalink level, and to use the information derived from such analysis to block access through a port where a host device is using a false, or spoofed, source IP address in transmitted data packets. The sensor produces an electrical signal responsive to seat belt tension, and the processing circuitry generates one of a specified number of messages pertaining to the range of the measured tension, and then modulates the current through the two wire interface to communicate the generated message to the occupant detection control module. The invention also provides compositions of A\u03b242 lowering agents and antioxidants, A\u03b242 lowering agents and non-selective secretase inhibitors, as well as A\u03b242 lowering agents and acetylcholinesterase inhibitors. A Panhard arm provides lateral stiffness and includes a first pivotal connection to the trailing arm and a second pivotal connection to a second suspension rail laterally spaced from the first suspension rail.