A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. Semiconductor-element mounting substrate sandwiches low-thermal-expansion substrate with upper interlayer resin layer and lower interlayer resin layer, and conductive circuit of organic substrate and first conductive circuit of low-thermal-expansion substrate are connected by via conductor formed in interlayer resin layer. Rotation of the transporter in front of a selected product engages a product delivery mechanism which gently and safely slides the product off the shelf onto the transporter. The monitoring window is shifted as a function of the ultrafiltration rate. The coverage of the light reflecting layer on the surface of the core particle is 70% or more. 0, it is provided that in a first process step argillaceous marl or a mixture of marl and clay having a basicity of <2.