A multi-interface point-to-point switching system, including a plurality of IO ports coupled to a plurality of respective devices, a switching fabric, a controller that determines the fixed, low latency signal path for each connection and commands the switching fabric to establish the determined signal path for each connection. The embedded memory includes a metal-oxide semiconductor capacitor and a metal-insulator-metal capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory. The plural code series generator includes a shift register having a plurality of shift stages in which a first initial value is loaded by the controller and adapted to be subject to a shift operation in synchronism with a clock.