Provided is a discrete time receiver having a structure capable of processing various broadband signals. The processor chip having the cache hit logic improves the reliability of a hit signal and operation speed is not limited. A p-side electrode is disposed on only a part of the upper surface of the p-InGaAsP contact layer so that a current non-injection area is formed on an area absent the p-side electrode. The digital data is placed into a frame for transmission over the interconnect. According to the present invention, a pattern is prepared in the step, comprising: forming a resist pattern; and coating the resist pattern-improving material on the surface of the resist pattern.