A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. When retrieving a document associated with the thumbnail, a document version is displayed that is more similar in appearance to the thumbnail than the original document. The coordinate positions of respective cell center positions are determined according to the calculation equations by applying the determined coefficients. The principles may also reduce the state and the overhead of maintaining the state in the network by removing the need to maintain at least one dedicated multicast tree per each MVPN. A gate dielectric layer is formed on the substrate to cover the gate.