1460414385-11062cc1-5134-4c4c-856e-4035dbd987f0

A method of optimizing clock-gated circuitry in an integrated circuit design is provided. The active network maintains an active set of connections that is at least as large as the active set maintained by the active terminal and does not initiate a connection termination if no confirmation of the channel allocation message is received. The input port is connected to a DC power line and a ground conductor on the circuit board.