According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory. The plating apparatus comprises a cassette stage for placing a substrate cassette thereon, a pre-treatment unit for pre-treating a surface of a substrate, and a plating unit for plating a surface of the substrate pre-treated in the pre-treatment unit. The trap body includes fins arrayed in a flow direction of the exhaust gas and having a surface on which a part of the by-products is deposited and trapped. The rotor also includes a plurality of apertures provided in the rotor valve surface and in communication with the flow paths for cyclically exposing the flow paths to the function compartments. The invention also relates to methods for producing this panel. The logic area includes salicided NMOS and PMOS gate electrodes and salicided sourcedrain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.