A data receiver circuit having a comparator that exhibits substantially variable offset that is controllable to represent a variable reference level, without a separate input to receive a reference voltage level. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-infirst-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-infirst-out memory logic components and to the plurality of synchronous random access memory blocks. A second hierarchy for the primary components of the primary hierarchy is provided.