A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external access conditions. At least one of the power and temperature levels may be compared to a lookup table containing predistortion coefficients. The invention also concerns constructs useful in the methods of the invention. Upon receipt of the generated broadcast start message from the time controller, the CAC processor calculates a capacity decrease due to broadcast service and subtracts the capacity decrease from the current available capacity to update the available capacity. The first power supply source voltage has a voltage level within a normal range required for normal operations of the internal device. A related method of manufacturing a fuel cell assembly is provided.