A CPU generates a real recording address y from y=n+m, where absolute time x is obtained from an ATIP decoder. The valve actuator apparatus includes a housing which defines an enclosure and a rim. Inclusive messages in the queue may be removed, replaced or aggregated, reducing the number of messages to be published when distribution limitations are no longer exceeded. A fill opening is located on the second panel and extends between the lateral sides and is disposed at a location adjacent the first closed end.